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REVISIONS LTR A DESCRIPTION Add packages T and W. Add vendor CAGE 60395 as source of supply. Increase data retention to 20 years, minimum. Redrawn with changes. Changes in accordance with NOR 5962-R139-94. Changes in accordance with NOR 5962-R278-94. Changes in accordance with NOR 5962-R163-96. Updated boilerplate. Added device types 16-18 and packages M and N to drawing along with vendor CAGE 0EU86 as supplier. Removed figures 9, 10 and 11 software data protect algorithms. Removed vendor 61395 as supplier. - glg Corrected dimensions for packages "M" and "N". - glg Added device 19, packages 6 and 7, and updated boilerplate. ksr DATE (YR-MO-DA) 93-06-29 APPROVED M. A. Frye
B C D E
94-03-29 94-09-19 96-06-27 98-07-22
M. A. Frye M. A. Frye M. A. Frye Raymond Monnin
F G
99-10-06 01- 10- 05
Raymond Monnin Raymond Monnin
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS OF SHEETS
G 35 G 15 G 36 G 16 G 37 G 17 G 18 G 19 G 20 G 21 G 1 G 22 G 2 G 23 G 3 G 24 G 4 G 25 G 5 G 26 G 6 G 27 G 7 G 28 G 8 G 29 G 9 G 30 G 10 G 31 G 11 G 32 G 12 G 33 G 13 G 34 G 14
REV SHEET
PREPARED BY Kenneth Rice CHECKED BY Charles Reusing
PMIC N/A
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216
APPROVED BY Charles E. Besore
MICROCIRCUIT, MEMORY, DIGITAL, CMOS 128K x 8 BIT EEPROM, MONOLITHIC SILICON
SIZE A
SHEET
DRAWING APPROVAL DATE 91-07-12 REVISION LEVEL G
CAGE CODE 67268
1 OF 37
5962-38267
DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E561-01
1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 | | | Federal stock class designator \ \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Software data protect yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes | | | RHA designator (see 1.2.1) 38267 01 | | | Device type (see 1.2.2) / Q | | | Device class designator (see 1.2.3) X | | | Case outline (see 1.2.4) X | | | Lead finish (see 1.2.5)
Device type 01,16 02 03,17 04 05,18 06 07,19 08 09 10 11 12 13 14 15
Generic number 1/
Circuit function 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM 128K x 8 EEPROM
Access time 250 ns 250 ns 200 ns 200 ns 150 ns 150 ns 120 ns 120 ns 90 ns 90 ns 70 ns 70 ns 120 ns 90 ns 70 ns
Write speed 10 ms 5 ms 10 ms 5 ms 10 ms 5 ms 10 ms 3 ms 10 ms 3 ms 10 ms 3 ms 3 ms 3 ms 3 ms
Write mode Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page Byte/Page
Endurance 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle 10,000 cycle
1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class M Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535
Q or V
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in QML-38535 and MIL-HDBK-103. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter X Y Z U T W M N 6 7 Descriptive designator GDIP1-T32 or CDIP2-T32 CQCC1-N44 See figure 1 CQCC1-N32 See figure 1 See figure 1 See figure 1 See figure 1 See figure 1(enhanced rad tolerant) See figure 1(enhanced rad tolerant) Terminals 32 44 32 32 30 36 32 32 32 32 Package style Dual in-line Square chip carrier Flat package Rectangular chip carrier Grid array Grid array Flat package Flat package Flat package Flat package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating case temperature range . . . . . . . . . . . . . . . . . . . . . . Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . Thermal resistance, junction-to-case (JC): Cases X, Y and U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cases T and W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum power dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . Junction temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Recommended operating conditions. Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltage (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level input voltage range (VIH) . . . . . . . . . . . . . . . . . . . . . . Low level input voltage range (VIL) . . . . . . . . . . . . . . . . . . . . . . Case operating temperature range (TC) . . . . . . . . . . . . . . . . . . 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . . . . . . . . . . . . . . 100 percent 4.5 V dc minimum to 5.5 V dc maximum 0.0 V dc 2.0 V dc to VCC + 1.0 V dc 6/ -0.1 V dc to 0.8 V dc -55(C to +125(C -0.5 V dc to +6.0 V dc 3/ -55(C to +125(C -65(C to +150(C +300(C See MIL-STD-1835 21(C/W 4/ 18(C/W 4/ 3(C/W 4/ 2(C/W 4/ 1.5(C/W 4/ 1.5(C/W 4/ 1.0 watts +175(C 5/ 10,000 cycles/byte (minimum) 20 years minimum
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltages referenced to VSS (VSS = ground), unless otherwise specified. 3/ Negative undershoots to a minimum of -1.0 V are allowed with a maximum of 20 ns pulse width. 4/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 6/ For device types 16-19 only, VIH on R shall be VCC - 0.5 V min. to VCC + 1.0 V max. E S SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. Test Method Standard Microcircuits. Interface Standard for Microcircuit Case Outlines.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192-88
-
Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, PA 19103). ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - I/C Latch-up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201). (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.
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3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 3 herein. When required, in screening (see 4.2 herein), or quality conformance inspection groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test in a checkerboard or similar pattern (a minimum of 50 percent of the total number of bits programmed). 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this document.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
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3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 41 (see MIL-PRF-38535, appendix A).
3.11 Processing of EEPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Conditions of the supplied devices. Devices will be supplied in an unprogrammed or clear state. No provision will be made for supplying programmed devices. 3.11.2 Erasure of EEPROMs. When specified, devices shall be erased in accordance with procedures and characteristics specified in 4.5.1. 3.11.3 Programming of EEPROMs. When specified, devices shall be programmed in accordance with procedures and characteristics specified in 4.5.2. 3.11.4 Verification of state of EEPROMs. When specified, devices shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be removed from the lot or sample. 3.11.5 Power supply sequence of EEPROMs. In order to reduce the probability of inadvertant writes, the following power supply sequences shall be observed. a. For device types 1-19, a logic high state shall be applied to W E and/or CE at the same time or before the application of VCC. For device types 16-19, an additional precaution is available, a logic low state shall be applied to RE S at the same time or before the application of VCC. b. For device types 1-19, a logic high state shall be applied to W E and/or CE at the same time or before the removal of VCC. For device types 16-19, an additional precaution is available, a logic low state shall be applied to RE S at the same time or before the removal of VCC. 3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data. 3.13 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data.
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4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MILPRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. b. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. Prior to burn-in, the devices shall be programmed (see 4.5.2 herein) with a checkerboard pattern or equivalent (manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit pattern). The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in shall constitute a device failure and shall be included in the PDA calculation and shall be removed from the lot. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (1) d. e. Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1c herein).
c.
Interim and final electrical parameters shall be as specified in table IIA herein. After the completion of all screening, the device shall be erased and verified prior to delivery.
4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MILSTD-883. Interim and final electrical test parameters shall be as specified in table IIA herein. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B of MIL-PRF-38535.
b. c.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
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TABLE I. Electrical performance characteristics. Test | |Symbol | | | | |IIH | | |IIL | | | | |IOZH | | | |IOZL | | | |VOH | | | |VOL | | | |VIH | | | |VIL | | |VH | | | | |ICC1 | | | | | | |ICC2 | | | | |ICC3 | | | | | Conditions | -55(C TC +125(C | VSS = 0 V; 4.5 V VCC 5.5 V | unless otherwise specified | |VCC = 5.5 V, VIN = 5.5 V | | |VCC = 5.5 V, VIN = 0.1 V | | | | | For R input E S | |VIH VCC OE |VCC = 5.5 V, VO = 5.5 V | | |VIH VCC OE |VCC = 5.5 V, VO = 0.0 V | | |IOH = -400 A, VCC = 4.5 V |VIH = 2.0 V, VIL = 0.8 V | | |IOL = 2.1 mA, VCC = 4.5 V |VIH = 2.0 V, VIL = 0.8 V | | |VCC = 5.5 V | | | |VCC = 4.5 V | | | | | | | |VCC = 5.5 V, WE = VIH, | |CE = OE = VIL |f = 1/tAVAV min | | | |VCC = 5.5 V, CE = VIH, | all I/O's = open, |OE = VIL, f = 0 Hz | | |VCC= 5.5 V, CE = VCC -0.3 V |Inputs = VIH, I/O's = open, |OE = VIL, f = 0 Hz | | | Group A |subgroups | | | | 1, 2, 3 | | | 1, 2, 3 | | | | | 1, 2, 3 | | | | 1, 2, 3 | | | | 1, 2, 3 | | | | 1, 2, 3 | | | | 1, 2, 3 | | | | 1, 2, 3 | | | 1, 2, 3 | | | | | 1, 2, 3 | | | | | | | 1, 2, 3 | | | | | 1, 2, 3 | | | | | Device | types | | | | All | | | All | | 16-19 | | | | | All | | | | | | All | | | | All | | | | 01-15 | | 16-19 | | All | | | 01-15 | | | 16-19 | 01-06, | 08,13, | 16,17 | 07,18, | 19 | 09-12, | 14,15 | | All | | | | | 01-07 | 08-12 | 13-15, | 16-19 | | Limits | | | Min | Max | | | | | -5 |5 | | | | | -5 |5 | | | -100 | 100 | | | | | -10 | 10 | | | | | | | -10 | 10 | | | | | | | 2.4 | | | | | | | | | 0.4 | | | | | | | 2.0 | 6.0 | | | 2.2 | 6.0 | | | -0.5 | 0.8 | | | | | 12 | 13 | | |VCC - |VCC + | 0.5 | 1.0 | | | | 80 | | | | 100 | | | | 120 | | | | | |3 | | | | | | | | | | 850 | | 500 | | 350 | | | | Unit | | | | | A | | | A | | | | | | | A | | | | | |V | | | |V | | | |V | | | |V | | |V | | | | | mA | | | | | | | mA | | | | | A | | |
High level input current Low level input current
High impedance output leakage current 1/
Output high voltage
Output low voltage
Input high voltage 2/
Input low voltage 2/ OE high voltage RE S high voltage Operating supply current
Standby supply current TTL
Standby supply current CMOS
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test | |Symbol | | | | |CIN | | | |COUT | | | | | | | | | |tAVAV | | | | | | | | |tAVQV | | | | | | | | | |tELQV | | | | | | | |tOLQV | | | |tELQX | | | |tEHQZ | | | | Conditions | -55(C TC +125(C | VSS = 0 V; 4.5 V VCC 5.5 V | unless otherwise specified | |VIN = 0 V, f = 1.0 MHz, |TC = +25(C, see 4.4.1c | | |VOUT = 0 V, f = 1.0 MHz |TC = +25(C, see 4.4.1c | | | See 4.4.1d | | | See figures 4, 5, and 6 as | applicable. 5/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group A |subgroups | | | |4 | | | |4 | | | | 7,8A,8B | | | | | |9, 10, 11 | | | | | | | | |9, 10, 11 | | | | | | | | | |9, 10, 11 | | | | | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | | Device | types | | | | All | | | | All | | | | All | | |01-02,16 |03-04,17 |05-06,18 | 07,08, | 13,19 | 09,10, | 14 | 11,12, | 15 | |01-02,16 |03-04,17 |05-06,18 | 07,08, | 13,19 | 09,10, | 14 | 11,12, | 15 | |01-02,16 |03-04,17 |05-06,18 | 07,08, | 13,19 | 09,10, | 14 | 11,12, | 15 | | 01-06 | 07-15 | 16-19 | | All | | | | 01-06 | 07-19 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limits | Min | | | | | | | | | | | | | | 250 | 200 | 150 | 120 | | 90 | | 70 | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 | | | | | | | | | Unit | Max | | | 10.0 | pF | | | 12.0 | pF | | | | | | | | | | ns | | | | | | 250 | 200 | 150 | 120 | ns | 90 | | 70 | | | 250 | 200 | 150 | 120 | ns | 90 | | 70 | | | 55 | ns 50 | 75 | | | ns | | | 55 | ns 50 | |
Input capacitance 3/ 4/
Output capacitance 3/ 4/
Functional tests
Read cycle time
Address access time
CE access time
OE access time
CE to output in low Z 4/ Chip disable to output in high Z 4/ See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test | |Symbol | | | | |tOLQX | | | |tOHQZ | | | |tAXQX | | | | | |tWHWL1 |tEHEL1 | | | | |tAVWL |tAVEL | | |tWLAX |tELAX | | | |tELWL |tWLEL | | |tWHEH |tEHWH | | |tOHWL |tOHEL | | |tWHOL |tEHOL | | |tWLWH |tELEH | | |tDVWH |tDVEH | | | | Conditions | -55(C TC +125(C | VSS = 0 V; 4.5 V VCC 5.5 V | unless otherwise specified | |See figures 4, 5, and 6 as | applicable. 5/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group A |subgroups | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | | |9, 10, 11 | | | | | | |9, 10, 11 | | | |9, 10, 11 | | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | | | Device | types | | | | All | | | | 01-06 | 07-19 | | | All | | | 01,03, | 05,07, | 09,11, | 16-19 | 02,04 | 06 | 08,10, | 12-15 | | All | | | 16-19 | 01-08, | 13 | 09-12, | 14,15 | | All | | | | All | | | | 01-15 | | 16-19 | | 01-15 | | 16-19 | | 01-15 | | 16-19 | 16-19 | 01-08, | 13 | 09-12, | 14,15 | | Limits | | | Min | Max | | | | |0 | | | | | | | | | 55 | | 50 | | | | |0 | | | | | | | | | | | 10 | | | | | |5 | |3 | | | | |0 | | | | | | 150 | | 70 | | | | | | 50 | | | |0 | | | | | | | |0 | | | | | | | | 10 | | | |0 | | | | 10 | | | |0 | | | | 100 | | | | 250 | | 100 | | 60 | | | | 40 | | | | | Unit | | | | | ns | | | | ns | | | | ns | | | | | | ms | | | | | | ns | | | | ns | | | | | ns | | | | ns | | | | ns | | | | ns | | | | ns | | | | ns | | |
OE to output in low Z 4/ Output disable to output in high Z 4/ Output hold from address change
Write cycle time
Address setup time
Address hold time
Write setup time
Write hold time
OE setup time
OE hold time
Write pulse width (page or byte write) Data setup time
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test | |Symbol | | | | |tWHDX |tEHDX | | |tWHWL2 | | | | | |tWHEL |tEHEL | | | | | | |tELWL | | | |tOVHWL | | | |tWLWH2 | | | |tWHEH | | | |tWHOH | | |VH | | | |tOLEL | | | |tDHWL | | | |tWHDX | | | | Conditions | -55(C TC +125(C | VSS = 0 V; 4.5 V VCC 5.5 V | unless otherwise specified | |See figures 4, 5, and 6 as | applicable. 5/ | | | | | | | | | | | | | | | | |See figures 4, 5, and 6 as | applicable. 5/ 6/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group A |subgroups | | | |9, 10, 11 | | | |9, 10, 11 | | | | | |9, 10, 11 | | | | | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | |9, 10, 11 | | | | Device | types | | | 01-07 | 16-19 | 08-15 | | | 01-15 | | 16-19 | |01-02,16 |03-04,17 |05-06,18 |07,08, |13,19 |09,10, |14 |11,12, |15 | | 01-15 | | | | 01-15 | | | 01-07 | | 08-15 | | | 01-15 | | | | 01-15 | | | 01-15 | | | | 01-15 | | | | 01-15 | | | | 01-15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limits | Min | Max | | 10 | 0 | | | .20 | 149 | .3 | 30 | | 250 | 200 | 150 | 120 | | 90 | | 70 | | 5 | | | | 5 | | | 10 | | 10 | | | 5 | | | | 5 | | | 12 | 13 | | | | 50 | | | 1 | | | | 1 | | | | | Unit | | | | | ns | | | | s | | | | | | | ns | | | | | | | s | | | | s | | | ms | | s | | | s | | | | s | | |V | | | | ms | | | | s | | | | s | |
Data hold time
Byte load cycle
Last byte loaded to data polling
CE setup time (chip erase) OE setup time (chip erase) WE pulse width (chip erase) CE hold time (chip erase) OE hold time (chip erase) High voltage (chip erase) Clear recovery (chip erase) Data setup time (chip erase) 7/ Data hold time during chip erase cycle 7/ See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. | |Symbol | | | | |tDFR | | | |tRR | | |tRP | | |tRES | | |tDB | | | Conditions | -55(C TC +125(C | VSS = 0 V; 4.5 V VCC 5.5 V | unless otherwise specified | |See figures 4, 5, and 6 as | applicable. 5/ 8/ | | | | | | | | | | | | | | | Group A |subgroups | | | |9, 10, 11 | | | |9, 10, 11 | | |9, 10, 11 | | |9, 10, 11 | | |9, 10, 11 | | | Device | types | | | | 16-19 | | | | 16-19 | | | 16-19 | | | 16-19 | | | 16-19 | | | | | | | | | | | | | | | | | | | | | | | | Unit | | | | | ns | | | | ns | | | s | | | s | | | ns |
Test
RE S low to output float
RE S to output delay Reset protect time
Reset high time
Time to device busy
Limits | Min | Max | | 0 | 350 | | | 0 | 450 | | 100 | | | 1.0 | | | 120 | |
1/ Connect all address inputs and OE to VIH and measure IOZL and IOZH with the output under test connected to VOUT. Terminal conditions for the output leakage current test shall be as follows: a. VIH = 2.0 V for device types 01-15 and 2.2 V for device types 16-19; VIL = 0.8 V. b. For IOZL: Select an appropriate address to acquire a logic "1" on the designated output. Apply VIH to C. E Measure the leakage current while applying the specified voltage. c. For IOZH: Select an appropriate address to acquire a logic "0" on the designated output. Apply VIH to C. E Measure the leakage current while applying the specified voltage. 2/ A functional test shall verify the dc input and output levels and applicable patterns as appropriate, all input and I/O pins shall be tested. Terminal conditions are as follows: a. Inputs: H =2.0 V for device types 01-15 and 2.2 V for device types 16-19; L = 0.8 V. Outputs: H = 2.4 V minimum and L = 0.4 V maximum. b. The functional tests shall be performed with VCC = 4.5 and VCC = 5.5 V. 3/ All pins not being tested are to be open. 4/ Tested initially and after any design or process changes which may affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 5/ Tested by application of specified timing signals and conditions. Equivalent ac test conditions: Output load, see figure 5; input rise and fall times 10 ns; input pulse levels, 0.4 V and 2.4 V; timing measurement reference levels, inputs, 1.5 V for device types 1-15 and 1 V and 2 V for device types 16-19; outputs, 1.5 V for device types 1-15 and 0.8 V and 2 V for device types 16-19. 6/ Chip erase functions are applicable to device types 01-15 only. 7/ This parameter not applicable for internal timer controlled devices. 8/ functions are applicable to device types 16-19 only. RE S
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4.4.1 Group A inspection. a. b. c. Tests shall be as specified in table IIA herein. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures and all input and output terminals tested. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device, these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M, procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference. All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified, (except devices submitted for groups C and D testing).
d.
e.
f.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. a. Steady-state life test conditions, method 1005 of MIL-STD-883: (1) (2) The device selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices shall be erased and verified (except devices submitted for group D testing). Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. TA = +125(C, minimum. Test duration: 1,000 hours, except as specified in method 1005 of MIL-STD-883.
(3) (4) b. c.
All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit pattern. After the completion of all testing, the devices shall be cleared and verified prior to delivery.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MILPRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. The devices selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices shall be erased and verified.
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Case T
FIGURE 1. Case outline.
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Case W
FIGURE 1. Case outline - Continued.
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Case Z
FIGURE 1. Case outline - Continued.
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Case Z Variations (all dimensions shown in inches) Symbol A b b1 C C1 D E E1 E2 E3 e H k k1 L Q S S1 N Min .090 .015 .015 .004 .004 .430 .330 .030 .050 BSC .008 1.228 .015 2, 5 2, 5 3 Max .120 .020 .019 .007 .006 .830 .488 .498 Notes 4
8
.025 ref .270 .026 .005 32 .370 .045 .045
6
Inches .004 .005 .006 .007 .008 .015 .019
mm 0.10 0.13 0.15 0.18 0.20 0.38 0.48
| | | | | | | |
Inches .020 .025 .026 .030 .045 .050 .120
mm 0.51 0.64 0.66 0.76 1.14 1.27 3.05
| | | | | | | |
Inches .270 .350 .370 .472 .488 .498 1.228
mm 6.86 8.89 9.40 11.99 12.40 12.65 31.19
NOTES: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Index area: An identification mark shall be located adjacent to pin 1 within the shaded area shown. Alternatively, a tab (dim k) may be used as shown. 3. Dimension Q shall be measured from the point on the lead located opposite the braze pad. 4. This dimension includes lid thickness. 5. Optional, see note 2. If pin 1 identification is used instead of this tab, the minimum dimension does not apply. 6. (N) indicates number of leads. 7. Uses a metal lid. 8. Includes braze fillet. 9. Metric equivalents are given for general information only. FIGURE 1. Case outline - Continued.
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Case M
Pin 1 indicator
FIGURE 1. Case outline - Continued.
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Case M Variations Millimeters Symbol Min A A1 b c D D2 E E1 e H L Q N 2.46 2.29 .038 0.08 20.57 18.92 10.80 8.38 1.14 25.40 7.37 0.66 Max 3.12 2.79 .048 0.18 21.08 19.18 11.30 9.04 1.40 27.94 7.87 0.94 32 Min .097 .090 .015 .003 .810 .745 .425 .330 .045 1.00 .290 .026 Max .123 .110 .019 .007 .830 .755 .445 .356 .055 1.10 .310 .037 Inches
NOTE:
Although dimensions are in inches, the US government preferred system of measurement is the metric SI system. However, since this item was originally designed using inch-pound units of measurement, in the event of conflict between the two, the inch-pound units shall take precedence. Metric equivalents are for general information only.
FIGURE 1. Case outline - Continued.
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Case N
Pin 1 indicator
FIGURE 1. Case outline - Continued.
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Case N Variations Millimeters Symbol Min A A1 b c D D1 D2 E E1 e H L Q N 3.18 2.29 0.38 0.08 20.57 19.69 18.92 10.80 7.37 1.14 25.40 7.37 0.66 Max 3.81 2.79 0.48 0.18 21.08 19.94 19.18 11.30 7.87 1.40 27.94 7.87 0.94 32 Min .125 .090 .015 .003 .810 .775 .745 .425 .290 .045 1.00 .290 .026 Max .150 .110 .019 .007 .830 .785 .755 .445 .310 .055 1.10 .310 .037 Inches
NOTE:
Although dimensions are in inches, the US government preferred system of measurement is the metric SI system. However, since this item was originally designed using inch-pound units of measurement, in the event of conflict between the two, the inch-pound units shall take precedence. Metric equivalents are for general information only.
FIGURE 1. Case outline - Continued.
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Case 6
FIGURE 1. Case outline - Continued.
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Case 6 Variations Millimeters Symbol Min A b c D E E1 E2 E3 e S1 L Q N 0.13 7.37 0.51 7.87 1.14 32 3.07 0.38 0.10 11.99 7.72 0.76 1.27 Max 3.81 0.56 0.18 21.08 12.40 7.87 Min .121 .015 .004 .472 .304 .030 .050 BSC .005 .355 .020 .375 .045 Max .150 .022 .009 .830 .488 .498 Inches
NOTE:
Although dimensions are in inches, the US government preferred system of measurement is the metric SI system. However, since this item was originally designed using inch-pound units of measurement, in the event of conflict between the two, the inch-pound units shall take precedence. Metric equivalents are for general information only. This package is manufactured for additonal Rad tolerant capabilities, contact the vendor for specific information.
FIGURE 1. Case outline - Continued.
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Case 7
FIGURE 1. Case outline - Continued.
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Case 7 Variations Millimeters Symbol Min A b c D E E1 E2 E3 e S1 L Q N 0.13 8.89 0.53 10.41 0.91 32 3.18 .038 0.08 10.26 5.94 0.76 1.27 Max 3.81 0.56 0.23 21.08 10.57 11.18 Min .117 .015 .003 .404 .234 .030 .050 BSC .005 .350 .021 .410 .036 Max .143 .022 .009 .830 .416 .440 Inches
NOTE:
Although dimensions are in inches, the US government preferred system of measurement is the metric SI system. However, since this item was originally designed using inch-pound units of measurement, in the event of conflict between the two, the inch-pound units shall take precedence. Metric equivalents are for general information only. This package is manufactured for additonal Rad tolerant capabilities, contact the vendor for specific information.
FIGURE 1. Case outline - Continued.
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Device types Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC = no connection NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A9 A8 A13 A14 NC W E VCC ------------------------NC NC NC NC A16 A15 A12 A7 A6 A5 NC NC NC A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE NC NC NC NC A11 A9 A8 A13 A14 NC NC W E VCC X, Z, U Y
01 - 15 W Terminal symbol NC NC NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A9 A8 A13 A14 NC NC NC W E VCC ----------------A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A9 A8 A13 W E VCC A15 A16 ----------------------------T U
16 - 19 M, N,6,7
RDY/B US Y A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A9 A8 A13 W E RE S A15 VCC -------------------------
RDY/B US Y A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A9 A8 A13 W E RE S A15 VCC -------------------------
FIGURE 2. Terminal connections.
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Device types 01-15 Mode Read Write Standby Write inhibit Write inhibit Write inhibit Write inhibit Software chip clear Software write protect High voltage chip clear CE VIL VIL VIH X VIH X VIL VIL VIL VIL OE VIL VIH X X X VIL VIL VIH VIH VH W E VIH VIL X VIH X X VIL VIL VIL VIL I/O DOUT DIN High Z DOUT or High Z High Z DOUT or High Z No operation DIN DIN VIH
VIH = High logic, "1" state, VIL = Low logic, "0" state. X = logic "don't care" state, High Z = high impedance state. VH = Chip clear voltage, DOUT = Data out, and DIN = Data in.
Device types 16-19 Mode Read Standby Write Deselect Write inhibit Write inhibit DA A polling T Program reset CE VIL VIH VIL VIL X X VIL X OE VIL X VIH VIH X VIL VIL X W E VIH X VIL VIH VIH X VIH X RE S VH X VH VH X X VH VIL RDY/B US Y High Z High Z High Z to VOL High Z ----VOL High Z I/O DOUT High Z DIN High Z ----DOUT (I/O7) High Z
.
VIH = High logic, "1" state, VIL = Low logic, "0" state. X = logic "don't care" state, High Z = high impedance state. DIN = Data in, DOUT = Data out, and VH = VCC-0.5 V to VCC+1.0 V.
FIGURE 3. Truth table.
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READ MODE WAVEFORM
NOTE: E S waveform is applicable to device types 16-19 only. R
FIGURE 4. Waveforms.
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WE CONTROLLED BYTE WRITE WAVEFORMS
NOTE: RDY/B US Y , E S , and VCC waveforms are applicable to device types 16-19 only. R
FIGURE 4. Waveforms.
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CE CONTROLLED BYTE WRITE WAVEFORMS
NOTE: RDY/B US Y , E S , and VCC waveforms are applicable to device types 16-19 only. R
FIGURE 4. Waveforms - Continued.
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PAGE WRITE MODE CYCLE WAVEFORMS
NOTE: RDY/B US Y , E S , and VCC waveforms are applicable to device types 16-19 only. R
FIGURE 4. Waveforms - Continued.
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CHIP ERASE WAVEFORMS (device types 01-15 only)
FIGURE 4. Waveforms - continued.
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NOTES: 1. VOH and VOL will be adjusted to meet load conditions of table I. 2. Use this circuit or equivalent circuit.
FIGURE 5. Switching load circuit.
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Line no. Test requirements Subgroups (per method 5005, table I) Device class M 1 2 3 4 5 6 7 8 Interim electrical parameters (see 4.2) Static burn-in I method 1015 Same as line 1 Dynamic burn-in (method 1015) Same as line 1 Final electrical parameters Group A test requirements Group C end-point electrical parameters Group D end-point electrical parameters Group E end-point electrical parameters 1*,2,3,7*, 8A,8B,9,10,11 1*,2,3,7*, 8A,8B,9,10,11 Required Required Not required Subgroups (per MIL-PRF-38535, table III) Device class Q 1,7,9 or 2,8A,10 Not required Device class V 1,7,9 or 1,2,8A,10 Required 1*,7*

Required 1*,7*
1*,2,3,7*, 8A,8B,9,10,11 1,2,3,4**,7, 8A,8B,9,10,11 1,2,3,7,8A,8B, 9,10,11 2,3,7, 8A,8B 1,7,9
1,2,3,4**,7,8A, 1,2,3,4**,7, 8B,9,10,11 8A,8B,9,10,11 2,3,7,8A,8B 1,2,3,7,8A,8B, 9,10, 11 2,3,7 8A,8B 1,7,9
9 10
2,3,7,8A,8B 1,7,9
1/ 2/ 3/ 4/ 5/ 6/ 7/
Blank spaces indicate test are not applicable. Any or all subgroups may be combined when using high-speed testers. Subgroups 7 and 8 functional tests shall verify the truth table. * Indicates PDA applies to subgroups 1 and 7. ** See 4.4.1c. Indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference to the previous interim electrical parameters (see line 1). See 4.4.1e. TABLE IIB. Delta limits at +25(C. Test 1/ ICC3 standby IIH, IIL IOHZ, IOLZ All device types 10% of specified value in table I 10% of specified value in table I 10% of specified value in table I
1/ The above parameters shall be recorded before and after the required burn-in and life tests to determine the delta .
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234 APR 97
A
REVISION LEVEL G
5962-38267
SHEET
34
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes M, Q, and V shall be as specified in MIL-PRF-38535. a. b. End-point electrical parameters shall be as specified in table IIA herein. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25(C 5(C, after exposure, to the subgroups specified in table IIA herein. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
c.
4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate figures and tables as follows. 4.5.1 Erasing procedures. The erasing procedures shall be as specified by the device manufacturer and shall be available upon request. 4.5.2 Programming procedure. The programming procedures shall be as specified by the device manufacturer and shall be made available upon request. 4.5.3 Software data protect procedures. The software data protect procedures shall be as specified by the device manufacturer and shall be made available upon request. 4.6 Delta measurements for device classes Q and V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices.
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234 APR 97
A
REVISION LEVEL G
5962-38267
SHEET
35
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF38535, MIL-STD-1331, and as follows: CIN, COUT . . . . . . GND . . . . . . . . . . . ICC . . . . . . . . . . . . IIL . . . . . . . . . . . . . IIH . . . . . . . . . . . . TC . . . . . . . . . . . . TA . . . . . . . . . . . . VCC . . . . . . . . . . . VH . . . . . . . . . . . . O/V . . . . . . . . . . . . Input and bidirectional output, terminal-to-GND capacitance. Ground zero voltage potential. Supply current. Input current low. Input current high. Case temperature. Ambient temperature. Positive supply voltage. Output enable and Write enable voltage during chip erase. Latchup over-voltage.
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. 6.5.2 Timing parameter abbreviations. All timing abbreviations use lower case characters with upper case subscripts. The initial character is always "t" and is followed by four descriptors. These characters specify two signal points arranged in a "from-to" sequence that define a timing interval. The two descriptors for each signal specify the signal name and the signal transition. Thus the format is: t Signal name from which interval is defined Transition direction for first signal Signal name to which interval is defined Transition direction for second signal a. Signal definitions: A = Address D = Data in Q = Data out W = Write enable E = Chip enable G = Output enable b. X X X X
Transition definitions: H = Transition to high L = Transition to low V = Transition to valid X = Transition to invalid or don't care Z = Transition to off (high impedance)
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234 APR 97
A
REVISION LEVEL G
5962-38267
SHEET
36
6.5.3 Waveforms. Waveform symbol Input MUST BE VALID CHANGE FROM H TO L CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED Output WILL BE VALID WILL CHANGE FROM H TO L WILL CHANGE FROM L TO H CHANGING STATE UNKNOWN HIGH IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA.
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234 APR 97
A
REVISION LEVEL G
5962-38267
SHEET
37
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN DATE: FINAL PRELIMINARY AS OF 2 OCT 01 Approved sources of supply for SMD 5962-38267 are listed below for immediate acquisition only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-BUL-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-BUL-103 and QML-38535. | Standard | microcircuit drawing | PIN 1/ | | 5962-3826701MXA | | | 5962-3826701MYA | | 5962-3826701MZA | 5962-3826701MZC | | | 5962-3826701MTA | | | 5962-3826701MUA | | 5962-3826701MWC | | | 5962-3826702MXA | | | 5962-3826702MYA | | | 5962-3826702MZA | | | 5962-3826702MWA | | 5962-3826703MXA | | | 5962-3826703MYA | | 5962-3826703MZA | 5962-3826703MZC | | | 5962-3826703MTA | | | 5962-3826703MUA | | 5962-3826703MWC | | | 5962-3826704MXA | | | 5962-3826704MYA | | Vendor | CAGE | number | | 1FN41 | 3/ | 3/ | 1FN41 | 3/ | 1FN41 | 3/ | 3/ | | 1FN41 | | | 1FN41 | | 3/ | 3/ | | 3/ | | | 3/ | | | 3/ | | | 3/ | | 1FN41 | 3/ | 3/ | 1FN41 | 3/ | 1FN41 | 3/ | 3/ | | 1FN41 | | | 1FN41 | | 3/ | 3/ | | 3/ | | | 3/ | | Vendor | similar | PIN 2/ | | AT28C010-25BM/883 | X28C010DMB-25 | CM28C010-250 | AT28C010-25LM/883 | LM28C010-250 | AT28C010-25FM/883 | X28C010FMB-25 | FM28C010-250 | | AT28C010-25UM/883 | | | AT28C010-25EM/883 | | X28C010KMB-25 | TM28C010-250 | | CM28C010H-250 | | | LM28C010H-250 | | | FM28C010H-250 | | | TM28C010H-250 | | AT28C010-20BM/883 | X28C010DMB-20 | CM28C010-200 | AT28C010-20LM/883 | LM28C010-200 | AT28C010-20FM/883 | X28C010FMB-20 | FM28C010-200 | | AT28C010-20UM/883 | | | AT28C010-20EM/883 | | X28C010KMB-20 | TM28C010-200 | | CM28C010H-200 | | | LM28C010H-200 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
See footnotes at end of list. 1 of 3
STANDARDIZED MILITARY DRAWING SOURCE APPROVAL BULLETIN - Continued. | | Standard | microcircuit drawing | PIN 1/ | | | 5962-3826704MZA | | | 5962-3826704MWA | | 5962-3826705MXA | | | 5962-3826705MYA | | 5962-3826705MZA | 5962-3826705MZC | | | 5962-3826705MTA | | | 5962-3826705MUA | | 5962-3826705MWC | | | 5962-3826706MXA | | | 5962-3826706MYA | | | 5962-3826706MZA | | | 5962-3826706MWA | | 5962-3826707MXA | | | | 5962-3826707MYA | | | | 5962-3826707MTA | | | 5962-3826707MUA | | | 5962-3826707MZA | 5962-3826707MZC | | | 5962-3826707MWC | | | | Vendor | CAGE | number | | | 3/ | | | 3/ | | 1FN41 | 60395 | 3/ | 1FN41 | 3/ | 1FN41 | 3/ | 3/ | | 1FN41 | | | 1FN41 | | 3/ | 3/ | | 3/ | | | 3/ | | | 3/ | | | 3/ | | 1FN41 | 60395 | 3/ | | 1FN41 | 3/ | | | 1FN41 | | | 1FN41 | | | 1FN41 | 3/ | 3/ | | 3/ | 3/ | | | Vendor | similar | PIN 2/ | | | FM28C010H-200 | | | TM28C010H-200 | | AT28C010-15BM/883 | X28C010DMB-15 | CM28C010-150 | AT28C010-15LM/883 | LM28C010-150 | AT28C010-15FM/883 | X28C010FMB-15 | FM28C010-150 | | AT28C010-15UM/883 | | | AT28C010-15EM/883 | | X28C010KMB-15 | TM28C010-150 | | CM28C010H-150 | | | LM28C010H-150 | | | FM28C010H-150 | | | TM28C010H-150 | | AT28C010-12BM/883 | X28C010DMB-12 | CM28C010-120 | | AT28C010-12LM/883 | LM28C010-120 | | | AT28C010-15UM/883 | | | AT28C010-15EM/883 | | | AT28C010-12FM/883 | X28C010FMB-12 | FM28C010-120 | | X28C010KMB-12 | TM28C010-120 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
See footnotes at end of list.
2 of 3
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN - Continued. | | Standard | microcircuit drawing | PIN 1/ | | | 5962-3826716QUA | 5962-3826716QMA | 5962-3826716QMC | 5962-3826716QNA | 5962-3826716Q6C | 5962-3826716Q7C | | | 5962-3826717QUA | 5962-3826717QMA | 5962-3826717QMC | 5962-3826717QNA | 5962-3826717Q6C | 5962-3826717Q7C | | | 5962-3826718QUA | 5962-3826718QMA | 5962-3826718QMC | 5962-3826718QNA | 5962-3826718Q6C | 5962-3826718Q7C | | | 5962-3826719QMC | 5962-3826719Q6C | 5962-3826719Q7C | | | Vendor | CAGE | number | | | 0EU86 | 0EU86 | 68911 | 0EU86 | 68911 | 68911 | | | 0EU86 | 0EU86 | 68911 | 0EU86 | 68911 | 68911 | | | 0EU86 | 0EU86 | 68911 | 0EU86 | 68911 | 68911 | | | 68911 | 68911 | 68911 | | | Vendor | similar | PIN 2/ | | | AS58C1001ECA-25/883C | AS58C1001F-25/883C | 28C010TFB-25 | AS58C1001SF-25/883C | 28C010TRPFB-25 | 28C011TRPFB-25 | | | AS58C1001ECA-20/883C | AS58C1001F-20/883C | 28C010TFB-20 | AS58C1001SF-20/883C | 28C010TRPFB-20 | 28C011TRPFB-20 | | | AS58C1001ECA-15/883C | AS58C1001F-15/883C | 28C010TFB-15 | AS58C1001SF-15/883C | 28C010TRPFB-15 | 28C011TRPFB-15 | | | 28C010TFB-12 | 28C010TRPFB-12 | 28C011TRPFB-12 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source. Vendor CAGE number 1FN41 Vendor name and address Atmel Corporation 2125 O'Nel Drive San Jose, CA 95131 Xicor, Incorporated 851 Buckeye Court Milpitas, CA 95035 Austin Semiconductor 8701 Cross Park Drive Austin, TX 78754-4566 Maxwell Technologies 9244 Balboa Avenue San Diego, CA 92123
60395
0EU86
68911
The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin.
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